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| Section I. HardCopy III Device Datasheet This section provides the datasheet for the HardCopy (R) III device family. This section includes the following chapter: Chapter 1, DC and Switching Characteristics of HardCopy III Devices Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. (c) December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 i-2 Section I: HardCopy III Device Datasheet HardCopy III Device Handbook, Volume 3 (c) December 2008 Altera Corporation 1. DC and Switching Characteristics of HardCopy III Devices HIII53001-2.0 Electrical Characteristics This chapter provides information about the absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for HardCopy (R) III devices. HardCopy III devices are offered in both commercial and industrial grades. Operating Conditions When HardCopy III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability, you must consider the operating requirements described in this chapter. HardCopy III devices are not speed binned like Stratix(R) III devices because HardCopy III devices are designed and built to function at a target frequency based on timing constraints, and operate at either commercial or industrial temperatures. Absolute Maximum Ratings Absolute maximum ratings define the maximum operating conditions for HardCopy III devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied by these conditions. Conditions beyond those listed in Table 1-1 can cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time can have adverse effects on the device. Table 1-1. HardCopy III Device Absolute Maximum Ratings - Preliminary (Part 1 of 2) (Note 1) Symbol VCCL VCC VCCD_PLL VCCA_PLL VCCPT (2) VCCPGM VCCPD VCCIO VCC_CLKIN VCCBAT (3) VI TJ IOUT Parameter Core voltage power supply I/O registers power supply PLL digital power supply PLL analog power supply Power supply for the temperature sensing diode Configuration pins power supply I/O pre-driver power supply I/O power supply Differential clock input power supply (top and bottom I/O banks only) Battery back-up power supply for design security volatile key register DC input voltage Operating junction temperature DC output current, per pin Minimum -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -- -0.5 -55 -25 Maximum 1.35 1.35 1.35 3.75 3.75 3.9 3.9 3.9 3.75 -- 4.0 125 40 Unit V V V V V V V V V V V C mA (c) December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 1-2 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Electrical Characteristics Table 1-1. HardCopy III Device Absolute Maximum Ratings - Preliminary (Part 2 of 2) (Note 1) Symbol TSTG Notes to Table 1-1: (1) Supply voltage specifications apply to voltage readings taken at the device pins and not the power supply. (2) In Stratix III devices, this power supply is also used for programmable power technology. (3) In HardCopy III devices, this power supply is not used. Parameter Storage temperature (no bias) Minimum -65 Maximum 150 Unit C Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage shown in Table 1-2 and undershoot to -2.0 V for input currents less than 100 mA and periods shorter than 20 ns. Table 1-2 lists the maximum allowed input overshoot voltage. The maximum allowed overshoot duration is specified as the percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. Table 1-2. Maximum Allowed Overshoot During Transitions - Preliminary Overshoot Duration as % of High Time 100.000 79.330 46.270 27.030 15.800 9.240 5.410 3.160 1.850 1.080 0.630 0.370 0.220 0.130 0.074 0.043 0.025 0.015 Symbol Parameter Condition 4 4.05 4.1 4.15 4.2 4.25 4.3 4.35 4.4 4.45 4.5 4.55 4.6 4.65 4.7 4.75 4.8 4.85 Unit % % % % % % % % % % % % % % % % % % Vi (AC) AC Input Voltage HardCopy III Device Handbook, Volume 3 (c) December 2008 Altera Corporation Chapter 1: DC and Switching Characteristics of HardCopy III Devices Electrical Characteristics 1-3 Figure 1-1 shows the methodology to determine the overshoot duration. The overshoot voltage is displayed in red and is present at the HardCopy III pin, up to 4.1 V. From Table 1-2, for an overshoot of up to 4.1 V, the percentage of high time for overshoot > 3.15 V can be as high as 46% over an 11.4 year period. The percentage of high-time is calculated as (delta T/T) x 100. This 11.4 year period assumes the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. For lower I/O toggle rates and situations where the device is in an idle state, lifetimes are increased. Figure 1-1. Overshoot Duration 4.1 V 3.15 V 3.0 V T T Recommended Operating Conditions This section lists the functional operation limits for AC and DC parameters for HardCopy III devices. The steady-state voltage and current values expected from HardCopy III devices are provided in Table 1-3. All supplies are required to monotonically reach their full-rail values within tRAMP maximum. Allowed ripple on power supplies is bounded by the minimum and maximum specifications listed in Table 1-3. Table 1-3. HardCopy III Device Recommended Operating Conditions - Preliminary (Part 1 of 2) Symbol VCCL (1) VCC (1) VCCD_PLL (1) VCCA_PLL VCCPT (2) Parameter Core voltage power supply for internal logic and input buffers I/O registers power supply PLL digital power supply PLL analog power supply Power supply for the temperature sensing diode Configuration pins power supply, 3.0 V VCCPGM Configuration pins power supply, 2.5 V Configuration pins power supply, 1.8 V Conditions -- -- -- -- -- -- -- -- Minimum 0.87 0.87 0.87 2.375 2.375 2.85 2.375 1.71 Typical 0.9 0.9 0.9 2.5 2.5 3.0 2.5 1.8 Maximum 0.93 0.93 0.93 2.625 2.625 3.15 2.625 1.89 Unit V V V V V V V V (c) December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 1-4 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Electrical Characteristics Table 1-3. HardCopy III Device Recommended Operating Conditions - Preliminary (Part 2 of 2) Symbol VCCPD (3) Parameter I/O pre-driver power supply, 3.0 V I/O pre-driver power supply, 2.5 V I/O power supply, 3.0 V I/O power supply, 2.5 V VCCIO I/O power supply, 1.8 V I/O power supply, 1.5 V I/O power supply, 1.2 V VCC_CLKIN Differential clock input power supply (top and bottom I/O banks only) Battery back-up power supply for design security volatile key register DC input voltage Output voltage Conditions -- -- -- -- -- -- -- -- Minimum 2.85 2.375 2.85 2.375 1.71 1.425 1.14 2.375 Typical 3.0 2.5 3.0 2.5 1.8 1.5 1.2 2.5 Maximum 3.15 2.625 3.15 2.625 1.89 1.575 1.26 2.625 Unit V V V V V V V V -- -- -- -- V VCCBAT (4) VI VO -- -- For commercial use For industrial use Normal POR (PORSEL=0) Fast POR (PORSEL=1) -0.3 0 0 -- -- -- 3.6 VCCIO 85 V V C TJ Operating junction temperature -40 50 s 50 s -- -- -- 100 300 ms 12 ms C -- -- tRAMP Power supply ramp time Notes to Table 1-3: (1) (2) (3) (4) In Stratix III devices, V CCL can also be 1.1 V, while VCC and VCCD_PLL are 1.1 V. In HardCopy III devices, all three supplies are 0.9 V. In Stratix III devices, this power supply is also used for programmable power technology. VCCPD is either 2.5 V or 3.0 V. For a 3.0-V I/O standard, VCCPD = 3.0 V. For a 2.5 V or lower I/O standard, VCCPD = 2.5 V. In HardCopy III devices, this power supply is not used. DC Characteristics This section lists the input pin capacitances, on-chip termination tolerance, and hot socketing specifications. Supply Current Standby current is the current the device draws after the device enters user mode with no inputs/outputs toggling and no activity in the device. Since these currents vary largely with the resources used, use the Excel-based Early Power Estimator (EPE) to get supply current estimates for your design. HardCopy III Device Handbook, Volume 3 (c) December 2008 Altera Corporation Chapter 1: DC and Switching Characteristics of HardCopy III Devices Electrical Characteristics 1-5 Table 1-4 lists supply current specifications for VCC_CLKIN and VCCPGM. Use the EPE to get supply current estimates for the remaining power supplies. Table 1-4. Supply Current Specifications for VCC_CLKIN and VCCPGM - Preliminary (Note 1) Symbol ICLKIN IPGM Note to Table 1-4: (1) Pending silicon characterization. Parameter VCC_CLKIN current specifications VCCPGM current specifications Min 0 0 Max TBD TBD Unit mA mA I/O Pin Leakage Current Table 1-5 defines HardCopy III I/O pin leakage current specifications. Table 1-5. HardCopy III I/O Pin Leakage Current - Preliminary (Note 1), (2) Symbol II IOZ Parameter Input pin leakage current Tri-stated I/O pin leakage current Conditions VI = VC CIOM AX to 0 V VO = VCC IOM AX to 0 V Min -10 -10 Typ -- -- Max 10 10 Unit A A Notes To Table 1-5: (1) This value is specified for normal device operation. The value may vary during power up. This applies for all VCC IO settings (3.0, 2.5, 1.8, 1.5, and 1.2 V). (2) The 10 mA I/O leakage current limit is applicable when the internal clamping diode is off. A higher current is observed when the diode is on. On-Chip Termination (OCT) Specifications If OCT calibration is enabled, calibration is automatically performed at power up for I/Os connected to the calibration block. Table 1-6 lists the HardCopy III OCT calibration block accuracy specifications. Table 1-6. HardCopy III On-Chip Termination Calibration Accuracy Specifications - Preliminary (Part 1 of 2) (Note 1) Calibration Accuracy Symbol 25- RS 3.0/2.5 50- RS 3.0/2.5 50- RT 2.5 25- RS 1.8 50- RS 1.8 50- RT 1.8 50- RS 1.5 Description Internal series termination with calibration (25- setting) Internal series termination with calibration (50- setting) Internal parallel termination with calibration (50- setting) Internal series termination with calibration (25- setting) Internal series termination with calibration (50- setting) Internal parallel termination with calibration (50- setting) Internal series termination with calibration (50- setting) Conditions VCC IO = 3.0/2.5 V VCC IO = 3.0/2.5 V VC CIO = 2.5 V VC CIO = 1.8 V VC CIO = 1.8 V VC CIO = 1.8 V VC CIO = 1.5 V Commercial (2) TBD TBD TBD TBD TBD TBD TBD Industrial -- -- -- -- -- -- -- Unit % % % % % % % (c) December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 1-6 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Electrical Characteristics Table 1-6. HardCopy III On-Chip Termination Calibration Accuracy Specifications - Preliminary (Part 2 of 2) (Note 1) Calibration Accuracy Symbol 50- RT 1.5 50- RS 1.2 50- RT 1.2 Notes to Table 1-6: (1) OCT calibration accuracy is valid at the time of calibration only. (2) Pending silicon characterization. Description Internal parallel termination with calibration (50- setting) Internal series termination with calibration (50- setting) Internal parallel termination with calibration (50- setting) Conditions VC CIO = 1.5 V VC CIO = 1.2 V VC CIO = 1.2 V Commercial (2) TBD TBD TBD Industrial -- -- -- Unit % % % The accuracy listed in Table 1-6 is valid at the time of calibration. If the voltage or temperature changes, the termination resistance value varies. Table 1-7 lists the resistance tolerance for HardCopy III on-chip termination. Table 1-7. On-Chip Termination Resistance Tolerance Specification for I/Os - Preliminary (Note 1) Resistance Tolerance Symbol ROCT_UNCAL ROCT_CAL Notes to Table 1-7: (1) Pending silicon characterization. (2) For resistance tolerance after power-up calibration, refer to Table 1-8. Description Internal series termination without calibration Internal series termination with calibration Commercial Max TBD (2) Industrial Max -- -- Unit % % Table 1-8 lists OCT variation with temperature and voltage after power-up calibration. Use Table 1-8 and Equation 1-1 to determine OCT variation without re-calibration. Equation 1-1. dR dR R O CT = R CAL 1 + ------ x T + ------ x V dT dV 1 Note that R CAL is calibrated on-chip termination at power-up. T and V are variations in temperature and voltage (VCCIO) at power-up. HardCopy III Device Handbook, Volume 3 (c) December 2008 Altera Corporation Chapter 1: DC and Switching Characteristics of HardCopy III Devices Electrical Characteristics 1-7 Table 1-8. On-Chip Termination Variation after Power-up Calibration - Preliminary (Note 1), (2) Symbol Description VCC IO (V) 3.0 2.5 dR/dV OCT variation with voltage without re-calibration 1.8 1.5 1.2 3.0 2.5 dR/dT OCT variation with temperature without re-calibration 1.8 1.5 1.2 Note to Table 1-8: (1) Valid for VC CIO range of 5% and temperature range of 0 to 85 C. (2) Pending silicon characterization. Commercial Typical TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Unit %/mV %/mV %/mV %/mV %/mV %/C %/C %/C %/C %/C Pin Capacitance Table 1-9 shows the HardCopy III device family pin capacitance. Table 1-9. HardCopy III Device Capacitance - Preliminary (Note 1) Symbol CIOTB CIOLR CC LKTB CCLK LR COUTFB CC LK1, CC LK3, CCLK8, and CCLK 10 Note to Table 1-9: (1) Pending silicon characterization. Parameter Input capacitance on top and bottom I/O pins Input capacitance on left and right I/O pins Input capacitance on top and bottom dedicated clock input pins Input capacitance on left and right dedicated clock input pins Input capacitance on dual-purpose clock output and feedback pins Input capacitance for dedicated clock input pins Typical TBD TBD TBD TBD TBD TBD Unit pF pF pF pF pF pF Hot Socketing Table 1-10 lists the hot socketing specifications for HardCopy III devices. Table 1-10. HardCopy III Hot Socketing Specifications - Preliminary (Note 1) Symbol IIOPIN(DC ) IIOPIN(A C) Note to Table 1-10: (1) Pending silicon characterization. Parameter DC current per I/O pin AC current per I/O pin Maximum 300 A 8 mA for 10 ns (c) December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 1-8 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Electrical Characteristics Internal Weak Pull-Up Resistor Table 1-11 lists the weak pull-up resistor values for HardCopy III devices. Table 1-11. HardCopy III Internal Weak Pull-Up Resistor - Preliminary (Note 1), (2) Symbol Parameter Value of I/O pin pull-up resistor before and during user mode, if the pull-up resistor option is enabled Conditions VCCIO = 3.0 V 5% (3) VCCIO = 2.5 V 5% (3) VCCIO = 1.8 V 5% (3) VCCIO = 1.5 V 5% (3) VCCIO = 1.2 V 5% (3) Notes to Table 1-11: (1) Pending silicon characterization. (2) All I/O pins have an option to enable weak pull-up except test and JTAG pins. (3) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO. Min -- -- -- -- -- Typ 25 25 25 25 25 Max -- -- -- -- -- Unit k k k k k RPU I/O Standard Specifications Table 1-12 through Table 1-17 list input voltage sensitivities (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for all I/O standards supported by HardCopy III devices. Refer to Table 1-33 on page 1-21 for an explanation of terms used in Table 1-12 through Table 1-17. VOL and VOH values are valid at the corresponding IOL and IOH , respectively. Table 1-12. Single-Ended I/O Standards Specifications -- Preliminary VCC IO (V) I/O Standard 3.0-V LVTTL 3.0-V LVCMOS 2.5V LVTTL/ LVCMOS 1.8V LVTTL/ LVCMOS 1.5 V LVTTL/ LVCMOS 1.2V LVTTL/ LVCMOS 3.0-V PCI 3.0-V PCI-X 1.71 1.425 1.14 2.85 2.85 Min 2.85 2.85 2.375 Typ 3 3 2.5 2.5 2.5 1.8 1.5 1.2 3 3 Max 3.15 3.15 2.625 2.625 2.625 1.89 1.575 1.26 3.15 3.15 VIL (V) Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -- -- Max 0.8 0.8 0.7 0.7 0.7 0.35 x VC CIO 0.35 x VC CIO 0.35 x VC CIO 0.3 x VC CIO 0.35 x VC CIO Min 1.7 1.7 1.7 1.7 1.7 0.65 x VCC IO 0.65 x VCC IO 0.65 x VCC IO 0.5 x VCC IO 0.5 x VCC IO VIH (V) Max 3.6 3.6 3.6 3.6 3.6 VC CIO + 0.3 VC CIO + 0.3 VC CIO + 0.3 3.6 -- VO L (V) Max 0.4 0.2 0.2 0.4 0.7 0.45 0.25 x VC CIO 0.25 x VC CIO 0.1 x VC CIO 0.1 x VC CIO VO H (V) Min 2.4 VCC IO - 0.2 2.1 2 1.7 VCC IO - 0.45 0.75 x VCC IO 0.75 x VCC IO 0.9 x VCC IO 0.9 x VCC IO IOL (mA) 2 0.1 0.1 1 2 2 2 2 1.5 1.5 IOH (mA) -2 -0.1 -0.1 -1 -2 -2 -2 -2 -0.5 -0.5 HardCopy III Device Handbook, Volume 3 (c) December 2008 Altera Corporation Chapter 1: DC and Switching Characteristics of HardCopy III Devices Electrical Characteristics 1-9 Refer to Figure 1-6 in the row "Single-Ended Voltage Referenced I/O Standard" in Table 1-33 for an example of a voltage referenced receiver input waveform and explanation of terms used in Table 1-13. Table 1-13. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications - Preliminary VCC IO (V) I/O Standard SSTL-2 CLASS I, II SSTL-18 CLASS I, II SSTL-15 CLASS I, II HSTL-18 CLASS I, II HSTL-15 CLASS I, II HSTL-12 CLASS I, II Min 2.375 1.71 1.425 1.71 1.425 1.14 Typ 2.5 1.8 1.5 1.8 1.5 1.2 Max 2.625 1.89 1.575 1.89 1.575 1.26 Min 0.49 x VCC IO 0.833 0.47 x VCC IO 0.85 0.68 0.47 x VCC IO VREF (V) Typ 0.5 x VC CIO 0.9 0.5 x VC CIO 0.9 0.75 0.5 x VC CIO Max 0.51 x VCC IO 0.969 0.53 x VCC IO 0.95 0.9 0.53 x VCC IO Min VREF - 0.04 VREF - 0.04 0.47 x VC CIO -- -- -- VTT (V) Typ VREF VREF VREF VC CIO/2 VC CIO/2 VC CIO/2 Max VREF + 0.04 VREF + 0.04 0.53 x VCC IO -- -- -- Table 1-14. Single-Ended SSTL and HSTL I/O Standards Signal Specifications - Preliminary (Part 1 of 2) VIL (D C) (V) I/O Standard SSTL-2 CLASS I SSTL-2 CLASS II SSTL-18 CLASS I SSTL-18 CLASS II SSTL-15 CLASS I SSTL-15 CLASS II HSTL-18 CLASS I HSTL-18 CLASS II HSTL-15 CLASS I HSTL-15 CLASS II Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max VREF - 0.15 VREF - 0.15 VREF - 0.125 VREF - 0.125 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VIH (D C) (V) Min VREF + 0.15 VREF + 0.15 VREF + 0.125 VREF + 0.125 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 Max VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.3 VIL(A C) (V) Max VREF - 0.31 VREF - 0.31 VREF - 0.25 VREF - 0.25 VREF - 0.175 VREF - 0.175 VREF - 0.2 VREF - 0.2 VREF - 0.2 VREF - 0.2 VIH(AC ) (V) Min VREF + 0.31 VREF + 0.31 VREF + 0.25 VREF + 0.25 VREF + 0.175 VREF + 0.175 VREF + 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.2 VO L (V) Max VTT - 0.57 VTT - 0.76 VTT - 0.475 0.28 0.2 x VC CIO 0.2 x VC CIO 0.4 0.4 0.4 0.4 VOH (V) Min VTT + 0.57 VTT + 0.76 VTT + 0.475 VC CIO - 0.28 0.8 x VC CIO 0.8 x VC CIO VC CIO - 0.4 VC CIO - 0.4 VC CIO - 0.4 VC CIO - 0.4 IO L (mA) 8.1 16.2 6.7 13.4 8 16 8 16 8 16 IOH (mA) -8.1 -16.2 -6.7 -13.4 -8 -16 -8 -16 -8 -16 (c) December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 1-10 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Electrical Characteristics Table 1-14. Single-Ended SSTL and HSTL I/O Standards Signal Specifications - Preliminary (Part 2 of 2) VIL (D C) (V) I/O Standard HSTL-12 CLASS I HSTL-12 CLASS II Min -0.15 -0.15 Max VREF - 0.08 VREF - 0.08 VIH (D C) (V) Min VREF + 0.08 VREF + 0.08 Max VCC IO + 0.15 VCC IO + 0.15 VIL(A C) (V) Max VREF - 0.15 VREF - 0.15 VIH(AC ) (V) Min VREF + 0.15 VREF + 0.15 VO L (V) Max 0.25 x VC CIO 0.25 x VC CIO VOH (V) Min 0.75 x VC CIO 0.75 x VC CIO IO L (mA) 8 16 IOH (mA) -8 -16 Refer to Figure 1-2 in the row "Differential I/O Standards" in Table 1-33 for receiver input and transmitter output waveforms, and for all differential I/O standards (LVDS, mini-LVDS, RSDS). VCC_CLKIN is the power supply for differential column clock input pins. VCCPD is the power supply for row I/Os and all other column I/Os. Table 1-15. Differential SSTL I/O Standard Specifications - Preliminary VC CIO (V) I/O Standard SSTL-2 CLASS I, CLASS II SSTL-18 CLASS I, CLASS II SSTL-15 CLASS I, CLASS II Min 2.375 Typ 2.5 Max 2.625 VSW ING (DC ) (V) Min 0.3 Max VCCIO + 0.6 VCCIO + 0.6 VX (A C) (V) Min V CCIO/2 - 0.2 V CCIO/2 - 0.175 VSW ING (AC ) (V) Max VCCIO/2 + 0.2 VCCIO/2 + 0.175 VOX (A C) (V) Min V CCIO/2 - 0.15 V CCIO/2 - 0.125 Typ -- Min 0.6 Max VCCIO Typ -- Max VCCIO/2 + 0.15 VCCIO/2 + 0.125 + 0.6 0.5 VCCIO 1.71 1.8 1.89 0.3 -- -- + 0.6 0.4 -- 1.425 1.5 1.575 0.2 -- -- VCCIO/2 -- -- VCCIO/2 -- Table 1-16. Differential HSTL I/O Standards Specifications - Preliminary VCC IO (V) I/O Standard HSTL-18 CLASS I, II HSTL-15 CLASS I, II HSTL-12 CLASS I, II Min 1.71 1.425 1.14 Typ 1.8 1.5 1.2 Max 1.89 1.575 1.26 VDIF(DC ) (V) Min 0.2 0.2 0.16 Max -- -- VC CIO + 0.3 Min 0.78 0.68 -- VX (A C) (V) Typ -- -- 0.5 x VC CIO Max 1.12 0.9 -- Min 0.78 0.68 0.4 x VCC IO VC M (D C) (V) Typ -- -- 0.5 x VC CIO Max 1.12 0.9 0.6 x VCC IO VD IF(AC ) (V) Min 0.4 0.4 0.3 Max -- -- VC CIO + 0.48 Table 1-17. Differential I/O Standard Specifications - Preliminary (Part 1 of 2) V C C IO (V) Max 2.625 2.625 Min 100 100 V (mV) ID V Max -- -- Min 0.05 (2) 1.05 (2) IC M (DC ) (V) Max 1.8 (2) 1.55 (2) Min 0.247 -- V (V) (1) OD V (V) (1) OCM I/O Standard Min 2.375 2.375 Typ 2.5 2.5 Condition V CM = 1.25V V CM = 1.25V Condition Dmax 700 Mbps Dmax > 700 Mbps Typ -- -- Max 0.6 -- Min 1.125 -- Typ 1.25 -- Max 1.375 -- 2.5V LVDS (Row I/O) HardCopy III Device Handbook, Volume 3 (c) December 2008 Altera Corporation Chapter 1: DC and Switching Characteristics of HardCopy III Devices Electrical Characteristics 1-11 Table 1-17. Differential I/O Standard Specifications - Preliminary (Part 2 of 2) V C C IO (V) Max 2.625 2.625 2.625 Min 100 100 100 V (mV) ID V Max -- -- -- Min 0.05 (2) 1.05 (2) 0.3 IC M (DC ) (V) Max 1.8 (2) 1.55 (2) 1.4 Min 0.247 -- 0.1 V (V) (1) OD V (V) (1) OCM I/O Standard Min 2.375 2.375 2.375 Typ 2.5 2.5 2.5 Condition V CM = 1.25V V CM = 1.25V V CM = 1.25V Condition Dmax 700 Mbps Dmax > 700 Mbps -- Typ -- -- 0.2 Max 0.6 -- 0.6 Min 1.0 -- 0.5 Typ 1.25 -- 1.2 Max 1.5 1.5 1.4 2.5V LVDS (Column I/O) RSDS (Row I/O) RSDS (Column I/O) Mini-LVDS (Row I/O) Mini-LVDS (Column I/O) LVPECL (3) 2.375 2.5 2.625 100 V CM = 1.25V -- 0.3 -- 1.4 0.1 0.2 0.6 0.5 1.2 1.5 2.375 2.5 2.625 200 -- 600 0.4 -- 1.325 0.25 -- 0.6 0.5 1.2 1.4 2.375 2.5 2.625 200 -- 600 0.4 -- Dmax 700 Mbps Dmax 700 Mbps 1.325 0.25 -- 0.6 0.5 1.2 1.5 2.375 (4) -- 2.5 (4) -- 2.625 (4) -- 300 -- -- -- -- -- 0.6 0.6 1.8 (5) 1.6 (5) -- -- -- -- -- -- -- -- -- -- -- -- Notes to Table 1-17: (1) RL range: 90 RL 110 . (2) For data rate: Dma x > 700 Mbps, the minimum input voltage is 1.0 V, the maximum input voltage is 1.6 V. For Dm ax 700 Mbps, the minimum input voltage is 0 V, the maximum input voltage is 1.85 V. (3) Column and Row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins. Differential clock inputs in column I/O use VCC_CLKIN which should be powered by 2.5 V. Differential clock inputs in row I/Os are powered by VCCPD. (4) Power supply for column I/O LVPECL differential clock input buffer is VCC _C LKIN. (5) For data rate Dm ax > 700 Mbps, the minimum input voltage is 0.85 V, and the maximum input voltage is 1.75 V. For data rate Dm ax 700 Mbps, the minimum input voltage is 0.45 V, and the maximum input voltage is 1.95 V. Power Consumption Altera offers two ways to estimate power for a design: the Excel-based Early Power Estimator and the Quartus(R) II PowerPlay Power Analyzer feature. Use the interactive Excel-based Early Power Estimator prior to designing in order to get a magnitude estimate of the device power. The Quartus II PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after the place-and-route is complete. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities which, combined with detailed circuit models, can yield very accurate power estimates. See Table 1-4 on page 1-5 for supply current estimates for VCCPGM and VCC_CLKIN . Use the EPE and PowerPlay Power Analyzer for current estimates of the remaining power supplies. f For more information about power estimation tools, refer to the Power Play Early Power Estimator User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II Device Handbook. (c) December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 1-12 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Switching Characteristics Switching Characteristics This section provides performance characteristics of HardCopy III core and periphery blocks for commercial grade devices. HardCopy III devices are designed to meet, at minimum, the -3 speed grade of the Stratix III devices. Silicon characterization determines the actual performance of the HardCopy III devices. These characteristics can be designated as Preliminary or Final, as defined below. Preliminary--Preliminary characteristics are created using simulation results, process data, and other known parameters. Final--Final numbers are based on actual silicon characterization and testing. These numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. Core Performance Specifications This sections describes the clock tree, phase-locked loop (PLL), digital signal processing (DSP), TriMatrix, configuration, and JTAG specifications. Clock Tree Specifications Table 1-18 lists clock tree performance specifications for the logic array, DSP blocks, and TriMatrix Memory blocks for HardCopy III devices. Table 1-18. HardCopy III Clock Tree Performance - Preliminary Device HC311 HC321 HC322 HC331 HC332 HC351 HC352 HC361 HC362 HC372 Note to Table 1-18: (1) Pending silicon characterization. (Note 1) Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Commercial Grade (MHz) 500 500 500 500 500 500 500 500 500 500 HardCopy III Device Handbook, Volume 3 (c) December 2008 Altera Corporation Chapter 1: DC and Switching Characteristics of HardCopy III Devices Switching Characteristics 1-13 PLL Specifications Table 1-19 describes the HardCopy III PLL specifications when operating in both the commercial junction temperature range (0 to 85 C) and the industrial junction temperature range (-40 to 100C). Refer to Figure 1-4 in the "PLL Specifications" row in Table 1-33 for a PLL block diagram. Table 1-19. HardCopy III PLL Specifications - Preliminary (Part 1 of 2) (Note 1) Symbol fIN fINPF D fVC O tEINDUTY fOUT fOUT_EXT tOUTDUTY tFC OMP tCONF IGPLL tCONF IGPHAS E fSC ANC LK tLOCK tDLOCK fCLB W Input clock frequency Input frequency to the PFD PLL VCO operating range Input clock or external feedback clock input duty cycle Output frequency for internal global or regional clock Output frequency for external clock output Duty cycle for external clock output (when set to 50%) External feedback clock compensation time Time required to reconfigure PLL scan chain Time required to reconfigure phase shift scanclk frequency Time required to lock from end of device power up (4) Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) PLL closed-loop low bandwidth PLL closed-loop medium bandwidth PLL closed-loop high bandwidth (5) tPLL_P SERR tARES ET tINCC J (4) tOUTPJ _DC (6) Accuracy of PLL phase shift Minimum pulse width on areset signal Input clock cycle to cycle jitter (FREF 100 MHz) Input clock cycle to cycle jitter (FREF < 100 MHz) Period jitter for dedicated clock output (FOUT 100 MHz) Period jitter for dedicate clock output (FOUT < 100 MHz) tOUTCC J_DC (6) Cycle to cycle jitter for dedicated clock output (FOUT 100 MHz) Cycle to cycle jitter for dedicated clock output (FOUT < 100 MHz) tOUTPJ _IO (6) tOUTCC J_IO (6) Period jitter for clock output on regular I/O (F OUT 100 MHz) Period jitter for clock output on regular I/O (FOUT < 100 MHz) Cycle to cycle jitter for clock output on regular I/O (FOUT 100 MHz) Cycle to cycle jitter for clock output on regular I/O (FOUT < 100 MHz) Parameter Min 5 5 600 40 -- -- 45 -- -- -- -- -- -- -- -- -- -- 10 -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 717 (2) 325 1300 60 717 (3) 717 (3) 55 10 -- -- 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit MHz MHz MHz % MHz MHz % ns scanclk cycles scanclk cycles MHz ms ms MHz MHz MHz ps ns UI (p-p) ps (p-p) ps (p-p) mUI (p-p) ps (p-p) mUI (p-p) ps (p-p) mUI (p-p) ps (p-p) mUI (p-p) (c) December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 1-14 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Switching Characteristics Table 1-19. HardCopy III PLL Specifications - Preliminary (Part 2 of 2) (Note 1) Symbol fDRIFT Parameter Frequency drift after PFDENA is disabled for duration of 100 ms Min -- Typ -- Max -- Unit % Notes to Table 1-19: (1) Pending silicon characterization. (2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard. (3) This specification is limited by the lower of the two: I/O fMAX or fOUT of the PLL. (4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps. (5) High bandwidth PLL settings are not supported in external feedback mode. (6) Peak-to-peak jitter with a probability level of 10-12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. DSP Block Specifications Table 1-20 describes the HardCopy III DSP performance specifications. Table 1-20. HardCopy III DSP Block Performance Specifications - Preliminary Mode 9 x 9-bit multiplier (a, c, e, g) (3) 9 x 9-bit multiplier (b, d, f, h) (3) 12 x 12-bit multiplier (a, e) (4) 12 x 12-bit multiplier (b, d, f, h) (4) 18 x 18-bit multiplier 36 x 36-bit multiplier Double mode 18 x 18-bit multiply adder 18 x 18-bit multiply adder 18 x 18-bit multiply adder with loop back (5) 18 x 18-bit multiply accumulator 18 x 18-bit multiply adder with chainout Input Cascade Independent output of 4 18 x 18 bit multiplier 36-bit shift (32 bit data) Notes to Table 1-20: (1) Maximum is for fully pipelined block with round and saturation disabled. (2) Pending silicon characterization. (3) The DSP block implements eight independent 9 x 9-bit multipliers using a, b, c, and d for the top half of the DSP block and e, f, g, and h for the bottom DSP half block multipliers. (4) The DSP block implements six independent 12 x 12-bit multipliers using a, b, and d for the top half of the DSP half block and e, f, and h for the bottom DSP half block multipliers. (5) Maximum for non-pipelined block with loopback input registers disabled with round and saturation disabled. (Note 1), (2) Number of Multipliers Max Unit 1 1 1 1 1 1 1 2 4 2 4 4 4 1 365 MHz 410 MHz 365 MHz 410 MHz 495 MHz 365 MHz 365 MHz 405 MHz 405 MHz 405 MHz 390 MHz 390 MHz 455 MHz 390 MHz HardCopy III Device Handbook, Volume 3 (c) December 2008 Altera Corporation Chapter 1: DC and Switching Characteristics of HardCopy III Devices Switching Characteristics 1-15 TriMatrix Memory Block Specifications Table 1-21 describes the HardCopy III TriMatrix memory block specifications. Table 1-21. HardCopy III TriMatrix Memory Block Performance Specifications - Preliminary (Part 1 of 2) (Note 1) Memory Block Type Single port 16 x 10 MLAB Simple dual-port 16 x 20 single clock ROM 64 x 10 ROM 32 x 20 Single-port 8K x 1 Single-port 4K x 2 or 2K x 4 Single-port 1K x 9, 512 x 18, or 256 x 36 Simple dual-port, 8K x 1 single clock Simple dual-port, 4K x 2 or 2K x 4, single clock Simple dual-port, 1K x 9, 512 x 18, or 256 x 36, single clock Simple dual-port, 8K x 1, 4K x 2, or 2K x 4 single clock, with the read-during-write option set to "Old Data" Simple dual-port, 1K x 9, 512 x 18, or 256 x 36, single clock, with the read-during-write option set to "Old Data" True dual-port, 8K x 1 single clock M9K True dual-port, 4K x 2 or 2K x 4, single clock True dual-port, 1K x 9 or 512 x 18, single clock True dual-port, 8K x 1, 4K x 2, or 2K x 4, single clock, with the read-during-write option set to "Old Data" True dual-port, 1K x 9 or 512 x 18, single clock, with the read-during-write option set to "Old Data" ROM 1P, 8K x 1, 4K x 2, or 2K x 4, single clock, with the read-during-write option set to "Old Data" ROM 1P, 1K x 9, 512 x 18, single clock, with the read-during-write option set to "Old Data" ROM 2P, 8K x 1, 4K x 2, or 2K x 4 ROM 2P, 1K x 9, or 512 x 18 Min Pulse Width (Clock High Time) Mode TriMatrix Memory 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- Max 500 500 500 500 465 485 475 460 480 475 312 312 440 480 460 295 285 485 485 485 485 800 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ps (c) December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 1-16 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Switching Characteristics Table 1-21. HardCopy III TriMatrix Memory Block Performance Specifications - Preliminary (Part 2 of 2) (Note 1) Memory Block Type True dual-port 4K x 36 dual clock Simple dual-port 16K x 9 or 8K x 18, dual clock Simple dual-port 4K x 36 or 2K x 72, dual clock ROM 1 Port ROM 2 Port M144K Single-port 16K x 9 or 8K x 18 Single-port 4K x 36 True dual-port 16K x 9, 8K x 18, or 4K x 36, dual clock with the read-during-write option set to "Old Data" Simple dual-port 16K x 9, 8K x 18, 4K x 36, or 2K x 72, dual clock with the read-during-write option set to "Old Data" Simple dual-port 2K x 64 dual clock (with ECC) Min Pulse Width (Clock High Time) Note to Table 1-21: (1) Pending silicon characterization. Mode True dual-port 16K x 9 or 8K x 18, dual clock TriMatrix Memory 1 1 1 1 1 1 1 1 1 1 1 -- Max 300 430 300 470 500 450 330 500 270 292 210 1000 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ps JTAG Specifications Table 1-22 shows the JTAG timing parameters and values for HardCopy III devices. Refer to Figure 1-3 in the "HIGH-SPEED I/O Block" row in Table 1-33 for JTAG timing requirements. Table 1-22. HardCopy III JTAG Timing Parameters and Values - Preliminary Symbol tJC P tJC H tJC L tJP SU (TDI) tJP SU (TMS) tJP H tJP CO tJP ZX tJP XZ TCK clock period TCK clock high time TCK clock low time JTAG port setup time for TDI JTAG port setup time for TMS JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Parameter Min 30 14 14 1 3 5 -- -- -- Max -- -- -- -- -- -- 11 14 14 Unit ns ns ns ns ns ns ns ns ns Periphery Performance This section describes the periphery performance, including high-speed I/O, external memory interface, and OCT calibration block specifications. HardCopy III Device Handbook, Volume 3 (c) December 2008 Altera Corporation Chapter 1: DC and Switching Characteristics of HardCopy III Devices Switching Characteristics 1-17 High-Speed I/O Specifications Refer to Table 1-33 for definitions of high-speed timing specifications. Table 1-23 shows the high-speed I/O timing for HardCopy III devices. Table 1-23. High Speed I/O Specifications - Preliminary Symbol fHSCLK (input clock frequency) (Note 1), (2), (3) Min 5 5 150 150 -- -- 150 -- -- Typ -- -- -- -- -- -- -- -- -- Max 625 600 717 1250 TBD (5) TBD (5) 1250 340 200 Unit MHz MHz MHz Mbps Mbps Mbps Mbps Mbps Mbps Conditions Clock boost factor W = 2 to 32 (4) Clock boost factor W = 1 (SERDES bypassed) Clock boost factor W = 1 (SERDES used) SERDES factor J = 3 to 10 Dedicate LVDS-fHSDR (data rate) Dedicated LVDS-f HSDRDPA (data rate) LVDS_E_3R-f HSDR LVDS_E_1R-f HSDR (data rate) Transmitter tX jitter Dedicated LVDS Output t RISE and tFALL tDUTY TCCS DPA mode DPA run length Soft CDR mode Soft CDR jitter tolerance Soft CDR run length Soft-CDR PPM tolerance Non DPA mode Sampling window Notes to Table 1-23: SERDES factor J = 2, uses DDR registers SERDES factor J = 1, uses SDR register -- -- -- Total jitter for data rate, 600 Mbps - 1.25 Gbps Total jitter for data rate, < 600 Mbps All differential I/O standards TX output clock duty cycle All differential I/O standards -- -- -- 45 -- -- -- -- 50 -- 160 0.1 200 55 100 ps UI ps % ps -- -- -- (5) UI -- -- -- -- -- -- -- -- -- (5) (5) (5) ps UI PPM All differential I/O standards -- -- (5) ps (1) When J = 3 to 10, the serializer/deserializer (SERDES) block is used. (2) When J = 1 or 2, the SERDES block is bypassed. (3) The minimum specification is dependent on the clock source (PLL and clock pin, for example) and the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not have a minimum toggle rate. (4) The input clock frequency and the W factor must satisfy the following Left and Right PLL output frequency specification: 150 MHz input clock frequency x W 1250 MHz. (5) Pending silicon characterization. (c) December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 1-18 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Switching Characteristics Table 1-24. DPA Lock Time Specifications - Preliminary Standard SPI-4 Parallel Rapid I/O Miscellaneous Note to Table 1-24: (1) Pending silicon characterization. (Note 1) Min TBD TBD TBD TBD TBD Typ -- -- -- -- -- Max -- -- -- -- -- Unit Number of repetitions Number of repetitions Number of repetitions Number of repetitions Number of repetitions Training Pattern 00000000001111111111 00001111 10010000 10101010 01010101 Transition Density 10% 25% 50% 100% 100% External Memory Interface Specifications Table 1-25 through Table 1-30 list the external memory interface specifications for the HardCopy III device family. Use these tables to perform memory interface timing analysis. Table 1-25. HardCopy III Maximum Clock Rate Support for External Memory Interfaces with Half-Rate Controller - Preliminary (Note 1) (MHz) Memory Standards DDR3 SDRAM DDR2 SDRAM DDR SDRAM QDRII+ SRAM QDRII SRAM RLDRAM II Note to Table 1-25: (1) Pending silicon characterization. Top and Bottom I/O Banks TBD TBD TBD TBD TBD TBD Left and Right I/O Banks TBD TBD TBD TBD TBD TBD Table 1-26. HardCopy III Maximum Clock Rate Support for External Memory Interfaces with Full-Rate Controller - Preliminary (Note 1) (MHz) Memory Standards DDR2 SDRAM DDR SDRAM Note to Table 1-26: (1) Pending silicon characterization. Top and Bottom I/O Banks TBD TBD Left and Right I/O Banks TBD TBD HardCopy III Device Handbook, Volume 3 (c) December 2008 Altera Corporation Chapter 1: DC and Switching Characteristics of HardCopy III Devices Switching Characteristics 1-19 External Memory I/O Timing Specifications Table 1-27 and Table 1-28 list HardCopy III device timing uncertainties on the read and write data paths. Use these specifications to determine timing margins for source synchronous paths between the HardCopy III FPGA and the external memory device. Refer to Figure 1-5 in the "SW (sampling window)" row in Table 1-33. Table 1-27. Sampling Window (SW), Read Side - Preliminary (Note 1) Sampling Window (ps) Location (2) VIO VIO VIO VIO VIO HIO HIO HIO HIO HIO Notes to Table 1-27: (1) Pending silicon characterization. (2) VIO (vertical I/O) refers to I/Os in the top and bottom banks; HIO (horizontal I/O) refers to I/Os in the left and right banks. Memory Type DDR3 DDR2 DDR1 QDRII / II + RLDRAM II DDR3 DDR2 DDR1 QDRII / II + RLDRAM Setup TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Hold TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Table 1-28. Transmitter Channel-to-Channel Skew (TCCS), Write Side - Preliminary (Note 1) TCCS (ps) Location (2) VIO VIO VIO VIO VIO HIO HIO HIO HIO HIO Notes to Table 1-28: (1) Pending silicon characterization. (2) VIO (vertical I/O) refers to I/Os in the top and bottom banks; HIO (horizontal I/O) refers to I/Os in the left and right banks. Memory Type DDR3 DDR2 DDR1 QDRII / II + RLDRAM II DDR3 DDR2 DDR1 QDRII / II + RLDRAM II Lead TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Lag TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD (c) December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 1-20 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Switching Characteristics DLL and DQS Logic Block Specifications Table 1-29 describes the delay-locked loop (DLL) frequency range specifications for HardCopy III devices. Table 1-29. HardCopy III DLL Frequency Range Specifications - Preliminary (Note 1) Frequency Mode 0 1 2 3 4 5 6 Note to Table 1-29: (1) Pending silicon characterization. Frequency Range (MHz) TBD TBD TBD TBD TBD TBD TBD Resolution (Degrees) 22.5 30 36 45 30 36 45 Table 1-30 describes the DQS phase offset delay per setting for HardCopy III devices. Table 1-30. Average DQS Phase Offset Delay per Setting - Preliminary (Note 1), (2), (3), (4) Min 7 Notes to Table 1-30: (1) The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes 4 to 6. (2) The typical value equals the average of the minimum and maximum values. (3) The delay settings are linear with a cumulative delay variation of 20ps for all speed grades. (4) Pending silicon characterization. Typ 11 Max 15 Unit ps OCT Calibration Block Specifications Table 1-31 shows the on-chip termination calibration block specifications for HardCopy III devices. Table 1-31. On-Chip Termination Calibration Block Specification - Preliminary Symbol OCTUSRCLK tOCTC AL tOCTS HIFT tRS_RT Description Clock required by OCT calibration blocks Number of OCTUSRCLK clock cycles required for OCT RS and RT calibration Number of OCTUSRCLK clock cycles required for OCT code to shift out per OCT calibration block Time required to dynamically switch from RS to RT Min -- -- -- -- Typical -- 1000 28 2.5 Max 20 -- -- -- Unit MHz cycles cycles ns HardCopy III Device Handbook, Volume 3 (c) December 2008 Altera Corporation Chapter 1: DC and Switching Characteristics of HardCopy III Devices I/O Timing Model 1-21 Duty Cycle Distortion (DCD) Specifications Table 1-32 lists the worst case DCD for HardCopy III devices. Detailed information on duty cycle distortion are published after characterization. Table 1-32. Duty Cycle Distortion on HardCopy III I/O Pins - Preliminary (Note 1), (2) Symbol Output Duty Cycle Notes to Table 1-32: (1) Preliminary DCD specification applies to clock outputs from PLLs, global clock tree, IOE driving dedicated, and general purpose I/O pins. (2) Detailed DCD specifications pending silicon characterization. Min 45 Max 55 Unit % I/O Timing Model The I/O timing specifications for HardCopy III devices will be available in a future revision of the DC and Switching Characteristics chapter in volume 3 of the HardCopy III Device Handbook. Glossary Table 1-33 shows the glossary for this chapter. Table 1-33. Glossary Table Letter A B C D Subject -- -- -- Differential I/O Standards Figure 1-2. Receiver Input Waveforms Single-Ended Waveform Positive Channel (p) = VIH VID Single-Ended Waveform VCM VOD VCM Differential Waveform Ground VID Differential Waveform VID p- Transmitter Output Waveformsn = 0 V VOD VOD p-n=0V Negative Channel (n) = VIL Positive Channel (p) = VOH Ground Negative Channel (n) = VOL Definitions -- -- -- E F fHSCLK fHSDR fHSDRDPA G H -- -- HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency. HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (f HSDR = 1/TUI), non-DPA. HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (f HSDRDPA = 1/TUI), DPA. -- -- -- -- (c) December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 1-22 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Glossary Table 1-33. Glossary Table Letter I J J JTAG Timing Specifications Subject -- Figure 1-3. JTAG Timing Specifications TMS Definitions -- HIGH-SPEED I/O Block: Deserialization factor (width of parallel data bus). TDI tJCP tJCH tJCL t JPSU tJPH TCK tJPZX tJPCO tJPXZ TDO K L M N O P -- -- -- -- -- PLL Specifications -- -- -- -- -- The block diagram shown in the following figure highlights the PLL Specification parameters: Figure 1-4. Diagram of PLL Specifications (Note 1) Switchover CLKOUT Pins fOUT_EXT CLK fIN Core Clock N fINPFD PFD CP LF VCO fVCO Counters C0..C9 fOUT GCLK RCLK M Key Reconfigurable in User Mode External Feedback Note: (1) Core Clock can only be fed by dedicated clock input pins or PLL outputs. Q R RL -- -- Receiver differential input discrete resistor (external to HardCopy III device). HardCopy III Device Handbook, Volume 3 (c) December 2008 Altera Corporation Chapter 1: DC and Switching Characteristics of HardCopy III Devices Glossary 1-23 Table 1-33. Glossary Table Letter S Subject SW (sampling window) Definitions The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window. Figure 1-5. Timing Diagram Bit Time 0.5 x TCCS RSKM Sampling Window (SW) RSKM 0.5 x TCCS Single-ended Voltage Referenced I/O Standard The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. Once the receiver input has crossed the AC value, the receiver is changed to the new logic state. The new logic state is maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. Figure 1-6. Single-Ended Voltage Referenced I/O Standard VCCIO VOH VIH (AC ) VIH(DC) VREF VIL(DC) VIL(AC ) VOL VSS T tC TCCS (channel-tochannel-skew) tDUTY High-speed receiver and transmitter input and output clock period. The timing difference between the fastest and the slowest output edges, including t C O variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to Figure 1-5 under S in this table). HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock. Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t C/w) tFALL tINCCJ tOUTPJ_IO tOUTPJ_DC tRISE U -- Signal high-to-low transition time (80-20%) Cycle-to-cycle jitter tolerance on PLL clock input Period jitter on general purpose I/O driven by a PLL Period jitter on dedicated clock output driven by a PLL Signal low-to-high transition time (20-80%) -- (c) December 2008 Altera Corporation HardCopy III Device Handbook, Volume 3 1-24 Chapter 1: DC and Switching Characteristics of HardCopy III Devices Referenced Documents Table 1-33. Glossary Table Letter V VICM VID VDIF(AC) VDIF(DC) VIH VIH(AC) VIH(DC) VIL VIL(AC) VIL(DC) VOCM VOD W X Y Z W -- -- -- Subject VCM(DC) DC common mode input voltage. Input common mode voltage: The common mode of the differential signal at the receiver. Input differential voltage swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. AC differential input voltage: Minimum AC input differential voltage required for switching. DC differential input voltage: Minimum DC input differential voltage required for switching. Voltage input high: The minimum positive voltage applied to the input that will be accepted by the device as a logic high. High-level AC input voltage High-level DC input voltage Voltage input low: The maximum positive voltage applied to the input that will be accepted by the device as a logic low. Low-level AC input voltage Low-level DC input voltage Output common mode voltage: The common mode of the differential signal at the transmitter. Output differential voltage swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. HIGH-SPEED I/O BLOCK: Clock boost factor -- -- -- Definitions Referenced Documents This chapter references the following documents: Power Play Early Power Estimator User Guide PowerPlay Power Analysis chapter in volume 3 of the Quartus II Device Handbook Document Revision History Table 1-34 shows the revision history for this document. Table 1-34. Document Revision History Date and Document Version December 2008, v2.0 Changes Made Updated Table 1-3. Updated Table 1-19. Updated Table 1-23. Made minor editorial changes. Summary of Changes -- May 2008, v1.0 Initial release. -- HardCopy III Device Handbook, Volume 3 (c) December 2008 Altera Corporation |
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